1. Field of the Invention
The present invention relates to Bipolar Complementary Metal Oxide Semiconductor ("BiCMOS") processes and circuits created by such processes and more specifically for translating an output signal from a Current-Mode Logic ("CML") or an Emitter-Coupled Logic ("ECL") circuit to a signal that is compatible with CMOS or Transistor-Transistor Logic ("TTL") voltage levels.
2. Description of the Related Art
In high performance digital logic designs, speed and power are two of the most commonly used criteria for technology selection. Although the power dissipation in CMOS circuits implemented with CMOS Field Effect Transistors ("FETs") is very low, this is only true for CMOS circuits that are not switching at high speed rates. When CMOS circuits are fixed at a logic level, they do not conduct current, and therefore negligible power is consumed. But when a CMOS circuit is switching from one logic state to another, current flows briefly and power is consumed. Therefore, the lower speed logic may be designed with CMOS transistors to reduce the power consumption. The typical low logic level voltage for CMOS circuits is Vss, and the typical high logic level voltage for CMOS circuits is Vcc, where Vcc is typically a voltage between 3 V and 15 V, and Vss is typically ground. In the case of a TTL circuit, the low logic level voltage is Vss, and the high logic level voltage is Vcc minus a diode voltage drop. The power supply Vcc for TTL circuit is usually 5 V.
A faster speed logic may be designed with CML or ECL to improve circuit performance. CML uses non-saturating current-mode bipolar logic and can be implemented by limiting the current and voltage swings to ensure only active-mode bipolar junction transistor ("BJT") operation. Rather than being constructed around transistors that operate as simple "on" or "off" devices, the CML transistors are designed to operate at two different "on" conditions at closely spaced voltage levels. Therefore, high performance digital logic designs typically utilize CML, including ECL which is a type of CML. A typical low logic level voltage of a CML is Vcc-0.4 V, and a high logic level voltage is Vcc. For an ECL circuit, the low logic level voltage is typically Vcc-1.4 V , and the high logic level voltage is Vcc-0.7 V.
To interface a CML or an ECL circuit with a CMOS or a TTL circuit, the output signal from the CML or ECL circuit must be transformed to a signal which is compatible with CMOS or TTL voltage levels. The translation requires a logic level translator that consumes a significant amount of DC power.
FIG. 1 shows a conventional translator, a mirrored PMOS switch circuit 10, for translating input signals Vin and Vin/ having a small logic swing to output signals Vout and Vout/ having a large logic swing. Mirrored PMOS switch circuit 10 includes a bias stage (12a and 12b) having PMOS devices P12 and P18 and NMOS devices N12 and N18 and a switching stage 14 having PMOS devices P14 and P16 and NMOS devices N14 and N16. PMOS devices P12, P14, P16 and P18 receive input signals Vin and Vin/which are the output signals from a small logic swing circuit such as a CML or an ECL circuit. Output signals of mirrored PMOS switch circuit 10, Vout and Vout/, are connected to the drain of P16 and the drain of P14, respectively. It should be noted that a signal named XXX/ is a complimentary signal of XXX. For example, Vin/ is complimentary of Vin.
PMOS devices P12, P14, P16 and P18 operate in common source mode and switch complimentary currents into NMOS devices N12, N14, N16 and N18 connected to PMOS devices P12, P16, P14 and P18, respectively.
The operation of mirrored PMOS switch circuit 10 is illustrated below. If Vin is high and Vin/ is low, then P12 and P14 are off, and P16 and P18 are on. The current that flows through P18 flows through N18 and is mirrored to N16. While P14 is off, the current through N16 pulls the drain of N16 low. Thus, Vout/ is low. Since P12 is off, the current that flows through N12 is insignificant, and so is the current through N14. Since P16 is on, the drain of P16 is pulled high, and thus Vout is high.
To provide increased output drive capability at Vout and Vout/, the NMOS devices in the switching stage (N16, and N14) are usually scaled much larger than the devices in the bias stage (P12, N12, P18 and N18). By having N14 larger than N12 and N16 larger than N18, current multiplication can occur across the current-mirror interface from the bias stage to the switching stage (i.e., from N12 to N14 and from N18 to N16). The relative sizes may be characterized by a ratio of the two transistors channel widths (with the channel lengths of the two transistors' being the same). Although various ratios may be used, a typical device ratio for optimum operation is typically 1:4. Thus, for a ratio of 1:4, the device size (e.g. channel width) of N14 or N16 is four times that of P12 or P18. For this same ratio, the device size of N14 or N16 is also four times that of N12 or N18. This allows the current in the bias stage to be minimum while maximizing the current in the switching stage. The device size ratio will not typically be much larger than 1:4 because as the devices in the switching stage become large, the capacitance at node 12 or 18 and at nodes "a" and "b" increases. If the capacitance becomes too large, then node 12 or 18 may not be charged or discharged quickly enough to switch PMOS device P14 or P16 and nodes "a" and "b" may not be charged and discharged quickly enough to switch the currents in N14 or N16.
Mirrored PMOS switch circuit 10 of FIG. 1 has several disadvantages. First, if mirrored PMOS switch circuit 10 is used to translate a CML signal having a small logic swing to a signal having a large logic swing compatible with CMOS or TTL voltage levels, then a separate level shifter stage is required. PMOS devices P12, P14, P16 and P18 typically need at least about a volt across the gate and the source to conduct. Without a sufficient gate bias, PMOS devices P12, P14, P16 and P18 are not effective as switches. When the gate bias is not sufficient, PMOS devices P12, P14, P16 and P18 operate in a low gate voltage current source mode (i.e., in a linear region) even when they are on.
Because a CML circuit outputs voltages between Vcc and Vcc-0.4 V, if the signal from the CML circuit is directly connected to node 12 or 18, it does not provide enough voltage to turn on PMOS device P12, P14, P16 or P18. Therefore, mirrored PMOS switch circuit 10 requires a pair of level shifters. Each level shifter having an NPN transistor and a current source can be placed in parallel with its corresponding branch of the bias stage (12a or 12b). Node 12 can be connected to a node between the emitter of the NPN transistor and the current source of the first level shifter, and node 18 can be connected to a node between the emitter of the NPN transistor and the current source of the second level shifter.
Second, the operation of mirrored PMOS switch circuit 10 is strongly dependent on the PMOS device threshold voltage (V.sub.T) which is a function of the semiconductor manufacturing process and the circuit's operating temperature. To turn on a PMOS device, the input voltage must drop below V.sub.T relative to Vcc. In that instance, when the absolute value of Vin-Vcc or Vin/-Vcc is greater than 1 V, the PMOS devices connected to Vin or Vin/, respectively, turn on. When PMOS device P14 turns on, Vout/ becomes high. When PMOS 5 device P16 turns on, Vout becomes high. On the other hand, when the absolute value of Vin-Vcc or Vin/-Vcc is less than 1 V, the PMOS devices connected to Vin or Vin/, respectively, do not turn on.
V.sub.T may vary due to process variations--that is, variations in the semiconductor manufacturing process. Process characteristics may change among different integrated circuits (ICs), including mirrored PMOS switch circuits, if they are manufactured in different lots, if they are from different wafers in the same lot or if they are from different places across a given wafer. Because of the changes in the process, PMOS devices of a first mirrored PMOS switch circuit on one IC chip may have VT's that are substantially different from those of a second mirrored PMOS switch circuit on another IC chip although the V.sub.T 's of the PMOS devices in a given mirrored PMOS switch circuit are approximately the same since the devices are located in close proximity of each other and are from the same wafer. For example, the first mirrored PMOS switch circuit may have V.sub.T 's at 0.8 V . The second mirrored PMOS switch circuit may have PMOS V.sub.T 's at 1.0 V . If Vin-Vcc is 0.9 V , then while PMOS devices P12 and P14 of the first mirrored PMOS switch circuit turn on, PMOS devices P12 and P14 of the second mirrored PMOS switch circuit do not turn on. The term "turn on" is intended in a relative sense to describe the current in the device in question.
Finally, mirrored PMOS switch circuit 10 consumes a large amount of power. The devices in the bias stage can be scaled smaller than the devices in the switching stage to minimize power consumption. Nevertheless, to compensate for process variations and temperature variations (e.g. the changing of VT and gm with temperature), the overall current of mirrored PMOS switch circuit 10 needs to be high, resulting in high power consumption.
Now referring to FIG. 2, a biased inverter 20 is another prior art translator. Biased inverter 20 includes NPN emitter follower transistors T22, T24, T26 and T28 and complimentary input inverters P24, N24, P26 and N26 operating in mid-point bias condition which drive cross-coupled complimentary output inverters P22, N22, P28 and N28.
Bias inverter 20 of FIG. 2 has higher speed performance than mirrored PMOS switch circuit 10 of FIG. 1 and is less sensitive to temperature and process variance since the complimentary output inverters P22, N22, P28 and N28 are being constantly operated just around their input switching threshold as determined by the complimentary input inverters P24, N24, P26 and N26. Ideally, the devices of the complimentary input inverters are much smaller than those of the complimentary output inverters since most of the current in the complimentary input inverters is not used for switching but rather for generating a bias voltage. For optimum performance, the devices of the complimentary input inverters should match those of the complimentary output inverters (e.g., P24/N24=P28/N28, P26/N26=P22/N22) as close as possible so that the threshold voltages track.
The disadvantage of biased inverter 20 of FIG. 2 is that it also consumes a large amount of power. Biased inverter 20 draws significant amounts of static operating current that is a strong function of process, Vcc voltage and temperature. Thus, biased inverter 20 is not useful for power sensitive applications.
It would be advantageous to provide a translator having a reduced power consumption and having switching and drive characteristics that are immune from variations in Vcc voltage, temperature and manufacturing process.